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ADC12J1600 Datasheet(PDF) 43 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 43 Page - Texas Instruments |
43 / 98 page ![]() ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.7.2.6 Configurable Pre-Emphasis The high-speed serial-output drivers incorporate a configurable pre-emphasis feature. This feature allows the output drive waveform to be optimized for different PCB materials and signal transmission distances. The pre- emphasis setting is adjusted through the serializer pre-emphasis setting in register 0x040, bits 3 to 0. The default setting is 4d. Higher values will increase the pre-emphasis to compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. The pre-emphasis setting should be adjusted to optimize the eye-opening for the hardware configuration and line rates needed. 7.3.7.2.7 Serial Output-Data Formatting Output data is generated by the DDC then formatted according to the selected decimation and output rate settings. When less than the maximum of eight lanes are active, lanes are disabled beginning with the highest numerical lanes. For example when only two lanes are active, lanes 0 and 1 are active, while all higher lanes are inactive. Table 10. Parameter Definitions USER STANDARD PARAMETER DESCRIPTION CONFIGURED JESD204B LINK OR DERIVED PARAMETER D Decimation factor, determined by DMODE register User No DDR Serial line rate: 1 = DDR rate (2x), 0 = SDR rate (1x) User No P54 Enable 5/4 PLL to increase line rate by 1.25x. User No 0 = no PLL (1x), 1 = enable PLL (1.25x) K Number of frames per multiframe User Yes N Bits per sample (before adding control bits and tails bits) Derived Yes CS Control bits per sample Derived Yes Bits per sample (after adding control bits and tail bits). Must be a multiple of N’ Derived Yes 4. L Number of serial lanes Derived Yes F Number of octets (bytes) per frame (per lane) Derived Yes M Number of (logical) converters Derived Yes S Number of samples per converter per frame Derived Yes CF Number of control words per frame Derived Yes 1=High density mode (samples may be broken across lanes), 0 = normal HD Derived Yes mode (samples may not be broken across lanes) Legal adjustment step for K, to ensure that the multi-frame clock is a sub- KS Derived No harmonic of other internal clocks Table 11. Serial Link Parameters(1) USER SPECIFIED PARAMETERS DERIVED PARAMETERS OTHER INFORMATION DECIMATION LEGAL K BIT RATE / ADC DDR P54 N CS N’ L F M S KS FACTOR (D) RANGE CLOCK(2) 1 1 0 12 0 12 8 8 8 5 2 4-32 2x 4 1 0 15 1 16 5 4 2 5 4 8-32 2x 4 1 1 15 1 16 4 2 2 2 2 10-32 2.5x 8 0 0 15 1 16 5 4 2 5 2 6-32 1x 8 0 1 15 1 16 4 2 2 2 1 9-32 1.25x 8 1 0 15 1 16 3 8 2 5 2 4-32 2x 8 1 1 15 1 16 2 2 2 1 2 10-32 2.5x 10 0 0 15 1 16 4 2 2 2 4 12-32 1x 10 1 0 15 1 16 2 2 2 1 8 16-32 2x 16 0 0 15 1 16 3 8 2 5 1 3-32 1x 16 0 1 15 1 16 2 2 2 1 1 9-32 1.25x (1) In all modes: HD = 0 and CF = 0 (2) x = times (for example, 2x = 2-times) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: ADC12J1600 ADC12J2700 |
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