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ADC12J1600 Datasheet(PDF) 42 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 98 page  ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.3.7.1 The Digital Outputs The ADC12J1600 and ADC12J2700 output data is transmitted on up to eight high-speed serial-data lanes. The output data from the ADC or DDC is formatted to the eight lanes, 8b10b encoded, and serialized. Up to four different serial output rates are possible depending on the decimation mode setting: 1x, 1.25x, 2x, and 2.5x. In 1x mode, the output serializers run at the same bit rate as the frequency of the applied DEVCLK. In 1.25x mode, the output serializers run at a bit rate that is 1.25-times that of the applied DEVCLK, and so on. For example, for a 1.6-GHz input DEVCLK, the output rates are 1.6 Gbps in 1x mode, 2 Gbps in 1.25x mode, 3.2 Gbps in 2x mode and 4 Gbps in 2.5x mode. 7.3.7.2 JESD204B Interface Features and Settings 7.3.7.2.1 Scrambler Enable Scrambling randomizes the 8b10b encoded data, spreading the frequency content of the data interface. This reduces the peak EMI energy at any given frequency reducing the possibility of feedback to the device inputs impacting performance. The scrambler is disabled by default and is enabled via SCR (register 0x201, bit 7). 7.3.7.2.2 Frames Per Multi-Frame (K-1) The frames per multi-frame (K) setting can be adjusted within constraints that are dependant on the selected decimation (D) and serial rate (DDR) settings. The K-minus-1 (KM1) register setting (register 0x201, bits 6:2) must be one less than the desired K setting. 7.3.7.2.3 DDR The serial rate can be either 1ƒ(CLK) (DDR = 0) or 2ƒ(CLK) (DDR = 1). 7.3.7.2.4 JESD Enable The JESD interface must be disabled (JESD_EN is set to 0) while any of the other JESD parameters are changed. While JESD_EN is set 0 the block is held in reset and the serializers are powered down. The clocks for this section are also gated off to further save power. When the parameters have been set as desired the JESD block can be enabled (JESD_EN is set to 1). 7.3.7.2.5 JESD Test Modes Several different JESD204B test modes are available to assist in link verification and debugging. The list of modes follows. NOTE PRBS test signals are output directly, without 8b10b encoding. • Normal operation • PRBS7 test mode • PRBS15 test mode • PRBS23 test mode • Ramp test mode • Short or long transport-layer test mode • D21.5 test mode • K28.5 test mode • Repeated ILA test mode • Modified RPAT test mode • Serial-outputs differential 0 test mode • Serial-outputs differential 1 test mode 42 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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Similar Description - ADC12J1600_16 |
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