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ADC12J1600 Datasheet(PDF) 35 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 98 page  ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Table 4. Over-Range Monitoring Period OVR_N MONITORING PERIOD 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 ( −12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS). The OR_T0 threshold is embedded as the LSB along with the upper 15 bits of every complex I sample. The OR_T1 threshold is embedded as the LSB along with the upper 15 bits of every complex Q sample. 7.3.5 ADC Core Features 7.3.5.1 The Reference Voltage The reference voltage for the ADC12J1600 and ADC12J2700 devices is derived from an internal bandgap reference. A buffered version of the reference voltage is available at the VBG pin for user convenience. This output has an output-current capability of ±100 μA. The VBG output must be buffered if more current is required. No provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register settings. 7.3.5.2 Common-Mode Voltage Generation The internal reference voltage is used to generate a stable common-mode voltage reference for the analog Inputs and the DEVCLK and SYSREF differential-clock inputs. 7.3.5.3 Bias Current Generation An external bias resistor, in combination with the on-chip voltage reference is used to provide an accurate and stable source of bias currents for internal circuitry. Using an external accurate resistor minimizes variation in device power consumption and performance. 7.3.5.4 Full Scale Range Adjust The ADC input full-scale range can be adjusted through the GAIN_FS register setting (registers 0x022 and 0x023). The adjustment range is approximately 500 mVPP to 950 mVPP. The full-scale range adjustment is useful for matching the input-signal amplitude to the ADC full scale, or to match the full-scale range of multiple ADCs when developing a multi-converter system. 7.3.5.5 Offset Adjust The ADC-input offset voltage can be adjusted through the OFFSET_FS register setting (registers 0x025 and 0x026). The adjustment range is approximately 28 mV to –28 mV differential. NOTE Offset adjust has no effect when background calibration mode is enabled. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: ADC12J1600 ADC12J2700 |
Similar Part No. - ADC12J1600_16 |
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