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ADC12J1600 Datasheet(PDF) 34 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 98 page  FSR tot(J) (n 1) I(PP) IN V 1 RMS V 2 F u u S u ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com High-speed high-performance ADCs such as the ADC12J1600 and ADC12J2700 devices require a very-stable input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR. where • RMStot(J) is the RMS total of all jitter sources in seconds • VI(PP) is the peak-to-peak analog input signal • VFSR is the full-scale range of the ADC • n is the ADC resolution in bits • FIN is the maximum input frequency, in Hertz, at the ADC analog input (1) Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources, including that from the clock source, the jitter added by noise coupling at board level and that added internally by the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the externally-added input clock jitter and the jitter added by any circuitry to the analog signal. Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code other than the expected 2048 when both input pins are at the same potential. 7.3.4 Over-Range Function To ensure that system-gain management has the quickest-possible response time, a low-latency configurable over-range function is included. The over-range function works by monitoring the raw 12-bit samples exiting the ADC module. The upper 8 bits of the magnitude of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. The following table lists how a raw ADC value is converted to an absolute value for a comparison of the thresholds. ADC SAMPLE ADC SAMPLE UPPER 8 BITS USED FOR ABSOLUTE VALUE (OFFSET BINARY) (2's COMPLEMENT) COMPARISON 1111 1111 1111 (4095) 0111 1111 1111 (+2047) 111 1111 1111 (2047) 1111 1111 (255) 1111 1111 0000 (4080) 0111 1111 0000 (+2032) 111 1111 0000 (2032) 1111 1110 (254) 1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0) 0000 0001 0000 (16) 1000 0001 0000 (-2032) 111 1111 0000 (2032) 1111 1110 (254) 0000 0000 0000 (0) 1000 0000 0000 (-2048) 111 1111 1111 (2047) 1111 1111 (255) If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 threshold during the monitoring period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. The resulting over-range bits are embedded into the complex output data samples and output on OR_T0 and OR_T1. Table 3 lists the outputs, related data samples, threshold settings and the monitoring period equation. Table 3. Threshold and Monitor Period for Embedded OR Bits EMBEDDED OVER-RANGE MONITORING PERIOD ASSOCIATED THRESHOLD ASSOCIATED SAMPLES OUTPUTS (ADC SAMPLES) OR_T0 OVR_T0 In-Phase (I) samples 2OVR_N(1) OR_T1 OVR_T1 Quadrature (Q) samples (1) OVR_N is the monitoring period register setting. 34 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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