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ADC12J1600 Datasheet(PDF) 33 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 98 page  CLK+ CLK± C(couple) C(couple) ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.2.3 DC Coupled Input Usage When a DC-coupled signal source is used, the common mode voltage of the applied signal must be within a specified range (VCMI). To achieve this range, the common mode of the driver should be based on the VCMO output provided for this purpose. Full-scale distortion performance degrades as the input common-mode voltage deviates from VCMO. Therefore, maintaining the input common-mode voltage within the VCMI range is important. Table 2 lists the recommended amplifiers for DC-coupled usage or if AC-coupling with gain is required. Table 2. Amplifier Recommendations –3-dB BANDWIDTH (MHz) MIN GAIN (dB) MAX GAIN (dB) GAIN TYPE PART NUMBER 7000 16 16 Fixed LMH3401 2800 0 17 Resistor set LMH6554 2400 6 26 Digital programmable LMH6881 900 –1.16 38.8 Digital programmable LMH6518 7.3.2.4 Handling Single-Ended Input Signals The ADC12J1600 and ADC12J2700 devices have no provision to adequately process single-ended input signals. The best way to handle single-ended signals is to convert these signals to balanced differential signals before presenting the signals to the ADC. 7.3.3 Clocking The ADC12J1600 and ADC12J2700 devices have a differential clock input, DEVCLK+ and DEVCLK–, that must be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as shown in Figure 65. Figure 65. Differential Sample-Clock Connection The differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at the clock source of that 100- Ω characteristic impedance. The input clock line must be as short and direct as possible. The ADC12J1600 and ADC12J2700 clock input is internally terminated with an untrimmed 100- Ω resistance. Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range specified in the Electrical Characteristics table. The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J1600 and ADC12J2700 devices feature a duty-cycle clock-correction circuit which maintains performance over temperature. The ADC meets the performance specification when the input clock high times and low times are maintained as specified in the Electrical Characteristics table. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: ADC12J1600 ADC12J2700 |
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