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ADC12J1600 Datasheet(PDF) 32 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 98 page  VIN+ 50- Source VIN± 1:2 Balun C(couple) C(couple) R(VIN) ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Feature Description (continued) 7.3.2.1 Input Clamp The ADC12J1600 and ADC12J2700 maximum DC input voltage is limited to the range 0 to 2 V to prevent damage to the device. To help maintain these limits, an active input clamping circuit is incorporated which sources or sinks input currents up to ±50 mA. The clamping circuit is enabled by default and is controlled via the Input_Clamp_EN bit (register 0x034, bit 5). The protection provided by this circuit is limited as follows: • Shunt current-clamping is only effective for non-zero source impedances. • At frequencies above 3 GHz the clamping is ineffective because of the finite turn-on and turn-off time of the switch. With these limitations in mind, analysis has been done to determine the allowable input signal levels as a function of input frequency when the Input Clamp is enabled, assuming the source impedance matches the input impedance of the device (100- Ω differential). This information is incorporated in the Absolute Maximum Ratings table. 7.3.2.2 AC Coupled Input Usage The easiest way to accomplish SE-to-differential conversion for AC-coupled signals is with an appropriate balun. Figure 64. Single-Ended-to-Differential Signal Conversion With a Balun Figure 64 shows a generic depiction of a SE-to-differential signal conversion using a balun. The circuitry specific to the balun depends on the type of balun selected and the overall board layout. TI recommends that the system designer contact the manufacturer of the selected balun to aid in designing the best performing single-ended to differential conversion circuit using that particular balun. When selecting a balun, understanding the input architecture of the ADC is important. Specific balun parameters must be considered. The balun must match the impedance of the analog source to the on-chip 100- Ω differential input termination of the ADC12J1600 and ADC12J2700 devices. The range of this input termination resistor is described in the Electrical Characteristics table as the specification RID. Also, as a result of the ADC architecture, the phase and amplitude balance are important. The lowest possible phase and amplitude imbalance is desired when selecting a balun. The phase imbalance must be no more than ±2.5° and the amplitude imbalance must be limited to less than 1 dB at the desired input frequency range. Finally, when selecting a balun, the voltage standing-wave ratio (VSWR), bandwidth, and insertion loss of the balun must also be considered. The VSWR aids in determining the overall transmission line termination capability of the balun when interfacing to the ADC input. The insertion loss must be considered so that the signal at the balun output is within the specified input range of the ADC as described in the Electrical Characteristics table as the specification VID. Table 1 lists the recommended baluns for specific signal frequency ranges. Table 1. Balun Recommendations MINIMUM MAXIMUM IMPEDANCE RATIO PART NUMBER MANUFACTURER FREQUENCY (MHz) FREQUENCY (MHz) 4.5 3000 1:1 TC1-1-13MA+ Mini-Circuits 400 3000 1:2 B0430J50100AHF Anaren 30 1800 1:2 ADTL2-18+ Mini-Circuits 10 4000 1:2 TCM2-43X+ Mini-Circuits 32 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
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