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ADC12J1600 Datasheet(PDF) 30 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 30 Page - Texas Instruments |
30 / 98 page ![]() DDC DDC Bypass ADC VCM VCM CLK VCMO RBIAS± REF DEVCLK+ DEVCLK± SYSREF+ SYSREF± SYNC~/TMST+ SYNC~/TMST± SYNC~ SPI Interface Configuration Registers Overrange Detection OR_T0 OR_T1 SCLK SDI SDO RBIAS+ VBG TDIODE+ TDIODE± Buffer Clock Sync DS7+/NCO_2 DS7±/NCO_2 DS6+/NCO_1 DS6±/NCO_1 DS5+/NCO_0 DS5±/NCO_0 DS4+ DS4± DS3+ DS3± DS2+ DS2± DS1+ DS1± DS0+ DS0± SCS VIN+ VIN± ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7 Detailed Description 7.1 Overview The ADC12J1600 and ADC12J2700 devices are an ultra-wideband sampling and digital tuning subsystem. The devices combine a very-wideband and high sampling-rate ADC front-end with a configurable digital-down conversion block. This combination provides the necessary features to facilitate the development of flexible software-defined radio products for a wide range of communications applications. The ADC12J1600 and ADC12J2700 devices are based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture that results in very high sampling rate, very good dynamic performance, and relatively low-power consumption. This ADC core is followed by a configurable DDC block which is implemented on a small geometry CMOS. The DDC block provides a range of decimation settings that allow the product to work in ultra-wideband, wideband, and more-narrow-band receive systems. The output data from the DDC block is transmitted through a JESD204B-compatible multi-lane serial-output system. This system minimizes the number of data pairs required to convey the output data to the downstream processing circuitry. 7.2 Functional Block Diagram 30 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 |
Similar Part No. - ADC12J1600_16 |
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Similar Description - ADC12J1600_16 |
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