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ADC12J1600 Datasheet(PDF) 21 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 21 Page - Texas Instruments |
21 / 98 page ![]() Decimation Factor 0 4 8 12 16 20 24 28 32 8 9 10 11 D088 Decimation Factor 0 4 8 12 16 20 24 28 32 7 8 9 10 D093 Ambient Temperature (°C) -50 -25 0 25 50 75 100 45 50 55 60 65 70 75 80 D079 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) Input Frequency (MHz) 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 5 6 7 8 9 10 D075 Decimation Factor 0 4 8 12 16 20 24 28 32 40 50 60 70 80 90 100 D091 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) All Supply Voltage Variation from Nominal (%) -10 -5 0 5 10 45 50 55 60 65 70 75 80 D076 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. ADC12J2700 FIN = 2483 MHz ADC12J2700 DDC bypass mode FIN = 608 MHz Figure 9. SNR, SINAD, SFDR vs Decimation Setting Figure 10. SNR, SINAD, SFDR vs Supply Voltage ADC12J2700 DDC bypass mode FIN = 608 MHz ADC12J2700 DDC bypass mode Figure 11. SNR, SINAD, SFDR vs Temperature Figure 12. ENOB vs Input Frequency ADC12J2700 FIN = 608 MHz ADC12J2700 FIN = 2483 MHz Figure 13. ENOB vs Decimation Setting Figure 14. ENOB vs Decimation Setting Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: ADC12J1600 ADC12J2700 |
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