ADC12J1600_16 datasheet(20/98 Pages) TI1

Part #	ADC12J1600

Description	GSPS ADCs With Integrated DDC

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Manufacturer	TI1 [Texas Instruments]

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Input Frequency (MHz)

0

300

600

900 1200 1500 1800 2100 2400 2700 3000

45

50

55

60

65

70

75

80

D073

SNR (dBFS)

SINAD (dBFS)

SFDR (dBFS)

Decimation Factor

0

4

8

12

16

20

24

28

32

40

50

60

70

80

90

100

D086

SNR (dBFS)

SINAD (dBFS)

SFDR (dBFS)

Sampling Rate (MSPS)

1500

2000

2500

3000

0.1

0.2

0.3

0.4

0.5

0.6

D123

VA19

VA12

VD12

Sampling Rate (MSPS)

1500

2000

2500

3000

1

1.2

1.4

1.6

1.8

2

D124

Sampling Rate (MSPS)

1500

2000

2500

3000

45

50

55

60

65

70

75

80

D120

SNR (dBFS)

SINAD (dBFS)

SFDR (dBFS)

Sampling Rate (MSPS)

1500

2000

2500

3000

5

6

7

8

9

10

D122

ADC12J1600, ADC12J2700

SLAS969C – JANUARY 2014 – REVISED JULY 2015

www.ti.com

6.9 Typical Characteristics

Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =

Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle,

R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.

DDC bypass mode

FIN = 608 MHz

DDC bypass mode

FIN = 608 MHz

Figure 4. ENOB vs Sampling Rate

Figure 3. SNR, SINAD, SFDR vs Sampling Rate

DDC bypass mode

FIN = 608 MHz

DDC bypass mode

FIN = 608 MHz

Figure 5. Power Consumption vs Sampling Rate

Figure 6. Supply Current vs Sampling Rate

ADC12J2700

DDC bypass mode

ADC12J2700

FIN = 608 MHz

Figure 7. SNR, SINAD, SFDR vs Input Frequency

Figure 8. SNR, SINAD, SFDR vs Decimation Setting

20

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ADC12J1600 Datasheet(PDF) 20 Page - Texas Instruments

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