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ADC12J1600 Datasheet(PDF) 18 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
Download  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 18 Page - Texas Instruments

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
Timing Requirements (continued)
MIN
NOM
MAX
UNIT
SERIAL INTERFACE (REFER TO Figure 2)
ƒ(SCK)
Serial clock frequency(5)
20
MHz
t(PH)
Serial clock high time
20
ns
t(PL)
Serial clock low time
20
ns
tsu
Serial-data to serial-clock rising setup time(5)
10
ns
th
Serial-data to serial clock rising hold time(5)
10
ns
t(CSS)
SCS-to-serial clock rising setup time
10
ns
t(CSH)
SCS-to-serial clock falling hold time
10
ns
t(IAG)
Inter-access gap
10
ns
(5)
This parameter is specified by design and is not tested in production.
6.7 Internal Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK
td(A)
Sampling (aperture) delay
Input CLK transition to sampling instant
0.64
ns
t(AJ)
Aperture jitter
0.1
ps RMS
t(LAT)
ADC core latency. See (1)
Decimation = 1, DDR = 1, P54 = 0
64
t(DEVCLK)
CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION)
227 ×
Calibration = FG, T_AUTO=1
106
t(CAL)
Calibration cycle time
t(DEVCLK)
102 ×
Calibration = FG, T_AUTO=0
106
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
SYSREF to LMFC delay
td(LMFC)
Functional delay between SYSREF assertion
All decimation modes
40
t(DEVCLK)
latched and LMFC frame boundary(1)
LMFC to Frame Boundary delay - DDC
Bypass Mode
td(TX)
Functional delay from LMFC frame boundary
Decimation = 1, DDR = 1, P54 = 0
52.7
t(DEVCLK)
to beginning of next multi-frame in transmitted
data(2)
Decimation = 4, DDR = 1, P54 = 0
52.7
Decimation = 4, DDR = 1, P54 = 1
43.9
Decimation = 8, DDR = 0, P54 = 0
60.7
Decimation = 8, DDR = 0, P54 = 1
51.5
Decimation = 8, DDR = 1, P54 = 0
52.7
Decimation = 8, DDR = 1, P54 = 1
43.9
Decimation = 10, DDR = 0, P54 = 0
60.7
LMFC to frame boundary delay - decimation
Decimation = 10, DDR = 1, P54 = 0
52.7
modes
td(TX)
Functional delay from LMFC frame boundary
Decimation = 16, DDR = 0, P54 = 0
60.7
t(DEVCLK)
to beginning of next multi-frame in transmitted
Decimation = 16, DDR = 0, P54 = 1
51.5
data(2)
Decimation = 16, DDR = 1, P54 = 0
52.7
Decimation = 16, DDR = 1, P54 = 1
43.9
Decimation = 20, DDR = 0, P54 = 0
60.7
Decimation = 20, DDR = 1, P54 = 0
52.7
Decimation = 32, DDR = 0, P54 = 0
60.7
Decimation = 32, DDR = 0, P54 = 1
51.5
Decimation = 32, DDR = 1, P54 = 0
52.7
td(LMFC)
Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary
40
t(DEVCLK)
Multi-frame
t(ILA)
Duration of initial lane alignment sequence
4
clock cycles
(1)
Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).
(2)
The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.
18
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Product Folder Links: ADC12J1600 ADC12J2700


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