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ADC12J1600 Datasheet(PDF) 17 Page - Texas Instruments |
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ADC12J1600 Datasheet(HTML) 17 Page - Texas Instruments |
17 / 98 page ![]() ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Timing Requirements (continued) MIN NOM MAX UNIT JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1) SYSREF to LMFC delay Functional delay between SYSREF td(LMFC) All decimation modes 40 t(DEVCLK) assertion latched and LMFC frame boundary(1) LMFC to frame boundary delay - DDC bypass mode td(TX) Functional delay from LMFC frame boundary Decimation = 1, DDR = 1, P54 = 0 52.7 t(DEVCLK) to beginning of next multi-frame in transmitted data.(2) Decimation = 4, DDR = 1, P54 = 0 52.7 Decimation = 4, DDR = 1, P54 = 1 43.9 Decimation = 8, DDR = 0, P54 = 0 60.7 Decimation = 8, DDR = 0, P54 = 1 51.5 Decimation = 8, DDR = 1, P54 = 0 52.7 Decimation = 8, DDR = 1, P54 = 1 43.9 Decimation = 10, DDR = 0, P54 = 0 60.7 LMFC to frame boundary delay - decimation Decimation = 10, DDR = 1, P54 = 0 52.7 modes td(TX) Functional delay from LMFC frame boundary Decimation = 16, DDR = 0, P54 = 0 60.7 t(DEVCLK) to beginning of next multi-frame in Decimation = 16, DDR = 0, P54 = 1 51.5 transmitted data(2) Decimation = 16, DDR = 1, P54 = 0 52.7 Decimation = 16, DDR = 1, P54 = 1 43.9 Decimation = 20, DDR = 0, P54 = 0 60.7 Decimation = 20, DDR = 1, P54 = 0 52.7 Decimation = 32, DDR = 0, P54 = 0 60.7 Decimation = 32, DDR = 0, P54 = 1 51.5 Decimation = 32, DDR = 1, P54 = 0 52.7 tsu(SYNC~- SYNC~ to LMFC setup time(3) 40 F) Required SYNC~ setup time relative to the internal LMFC boundary. t(DEVCLK) th(SYNC~- SYNC~ to LMFC hold time(3) –8 F) Required SYNC~ hold time relative to the internal LMFC boundary. SYNC~ assertion time Frame clock t(SYNC~) 4 Required SYNC~ assertion time before deassertion to initiate a link resynchronization. cycles td(LMFC) Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary 40 t(DEVCLK) Multi-frame t(ILA) Duration of initial lane alignment sequence 4 clock cycles SYSREF tsu(SYS) Setup time SYSREF relative to DEVCLK rising edge(4) 40 ps th(SYS) Hold time SYSREF relative to DEVCLK rising edge (4) 40 ps t(PH_SYS) SYSREF assertion duration after rising edge event. 8 t(DEVCLK) t(PL_SYS) SYSREF deassertion duration after falling edge event. 8 t(DEVCLK) K × F × DDR = 0, P54 = 0 10 K × F × DDR = 0, P54 = 1 8 t(SYS) Period SYSREF± t(DEVCLK) K × F × DDR = 1, P54 = 0 5 K × F × DDR = 1, P54 = 1 4 (2) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present. (3) This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this parameter is not met the device will still function correctly but will not be aligned to other devices. (4) This parameter is specified by design, characterization, or both and is not tested in production. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: ADC12J1600 ADC12J2700 |
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