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ADC12J1600 Datasheet(PDF) 16 Page - Texas Instruments

Part # ADC12J1600
Description  GSPS ADCs With Integrated DDC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12J1600 Datasheet(HTML) 16 Page - Texas Instruments

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default
setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with
50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at TA = 25°C.
(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
PD = 0, calibration = FG, bypass DDC
454
493
I(VA19)
Analog 1.9-V supply current
PD = 0, calibration = BG, bypass DDC
553
591
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
553
598
PD = 0, calibration = FG, bypass DDC
180
222
I(VA12)
Analog 1.2-V supply current
PD = 0, calibration = BG, bypass DDC
190
233
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
196
243
PD = 0, calibration = FG, bypass DDC
225
460
I(VD12)
Digital 1.2-V supply current
PD = 0, calibration = BG, bypass DDC
237
529
mA
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
255
568
PD = 0, calibration = FG, bypass DDC
1.35
1.75
PD = 0, calibration = BG, bypass DDC
1.56
2.04
W
PC
Power consumption
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1
1.59
2.11
PD = 1
< 50
mW
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
DEVICE (SAMPLING) CLOCK
Sampling rate is equal to clock input, ADC12J2700
1
2.7
ƒ(DEVCLK)
Input DEVCLK frequency
GHz
Sampling rate is equal to clock input, ADC12J1600
1
1.6
td(A)
Sampling (aperture) delay
Input CLK transition to sampling instant
0.64
ns
t(AJ)
Aperture jitter
0.1
ps RMS
t(LAT)
ADC core latency(1)
Decimation = 1, DDR = 1, P54 = 0
64
t(DEVCLK)
Decimation = 4, DDR = 1, P54 = 0
292
Decimation = 4, DDR = 1, P54 = 1
284
Decimation = 8, DDR = 0, P54 = 0
384
Decimation = 8, DDR = 0, P54 = 1
368
Decimation = 8, DDR = 1, P54 = 0
392
Decimation = 8, DDR = 1, P54 = 1
368
Decimation = 10, DDR = 0, P54 = 0
386
Decimation = 10, DDR = 1, P54 = 0
386
t(LAT_DDC) ADC core and DDC latency
(1)
Decimation = 16, DDR = 0, P54 = 0
608
t(DEVCLK)
Decimation = 16, DDR = 0, P54 = 1
560
Decimation = 16, DDR = 1, P54 = 0
608
Decimation = 16, DDR = 1, P54 = 1
560
Decimation = 20, DDR = 0, P54 = 0
568
Decimation = 20, DDR = 1, P54 = 0
568
Decimation = 32, DDR = 0, P54 = 0
1044
Decimation = 32, DDR = 0, P54 = 1
948
Decimation = 32, DDR = 1, P54 = 0
1044
(1)
Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).
16
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Product Folder Links: ADC12J1600 ADC12J2700


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