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DM54L93 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DM54L93 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 4 page ![]() TLF6637 June 1989 DM54L93 Decade Divide-by-12 and Binary Counters General Description Each of these monolithic counters contains four master- slave flip-flops and additional gating to provide a divide-by- two counter and a three-stage binary counter for which the count cycle length is divide-by-eight To use their maximum count length (decade divide-by- twelve or four-bit binary) the B input is connected to the QA output The input count pulses are applied to input A and the outputs are as described in the appropriate truth table Features Y Typical power dissipation 16 mW Y Count frequency 15 MHz Connection Diagram Dual-In-Line Package TLF6637 – 1 Order Number DM54L93J or DM54L93W See NS Package Number J14A or W14B Function Tables COUNT SEQUENCE (See Note A) Count Output QD QC QB QA 0L L L L 1L L L H 2L L H L 3L L H H 4L H L L 5L H L H 6L H H L 7L H H H 8H L L L 9H L L H 10 H L H L 11 H L H H 12 H H L L 13 H H L H 14 H H H L 15 H H H H RESETCOUNT TRUTH TABLE (Note B) Reset Inputs Output R0(1) R0(2) QD QC QB QA HH L L L L L X COUNT X L COUNT Note A Output QA is connected to input B Note B H e High Level L e Low Level X e Don’t Care C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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