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M29F800DT Datasheet(PDF) 5 Page - STMicroelectronics |
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M29F800DT Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 39 page  5/39 M29F800DT, M29F800DB SUMMARY DESCRIPTION The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (5V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically ar- ranged, see Figures 5 and 6, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the ap- plication may be stored. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in SO44 and TSOP48 (12 x 20mm) packages. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names AI06148B 19 A0-A18 W DQ0-DQ14 VCC M29F800DT M29F800DB E VSS 15 G RP DQ15A–1 RB BYTE A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output (not available on SO44 package) BYTE Byte/Word Organization Select VCC Supply Voltage VSS Ground NC Not Connected Internally |
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