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TMC4210 Datasheet(PDF) 15 Page - TRINAMIC Motion Control GmbH & Co. KG. |
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TMC4210 Datasheet(HTML) 15 Page - TRINAMIC Motion Control GmbH & Co. KG. |
15 / 48 page ![]() TMC4210 DATASHEET (Rev. 1.03 / 2015-JUN-03) 15 www.trinamic.com 5.2.2.2 Datagrams Received by µC from the TMC4210 The datagrams received by the µC from the TMC4210 contain two groups of bits: STATUS BITS The status bits, sent back with each datagram, comprehend the most important internal status bits of the TMC4210 and the settings of the reference switches DATA BITS Data bits are only for write access. The most significant bit MSB is received first; the least significant bit LSB is received last. The TMC4210 only sends datagrams on demand. 32 BIT DATAGRAM SENT BACK FROM THE TMC4210 TO µC VIA PIN SDO_C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 STATUS BITS DATA BITS - - - STATUS INFORMATION BITS INT The status bit INT is the internal high active interrupt controller status output signal. Handling of interrupt conditions without using interrupt techniques is possible by polling this status bit. The interrupt signal is available multiplexed with the SPI read back data at the nINT_SDO_C pin of the TMC4210. The pin nINT_SDO_C may additionally be connected to an interrupt input of the microcontroller. Do not set SDO_INT=1 because this setting disables the SPI output. Since the SDO_C / nINT output on TMC4210-I is multiplexed, the microcontroller has to disable its interrupt input while it sends a datagram to the TMC4210. The SDO_C signal driven by the TMC4210 alternates during datagram transmission. R_L The status bit R_L represents the state of the left reference switch input (r_l). R_R r_r is visible here only, while mot1R has not yet been set. GP_IN The GP_IN status bit represents the setting of the general purpose input. Refer to chapter 6.1.10.2, too. xEQt1 The status bit xEQt1 indicates for the stepper motor, if it has reached its target position. The status bits r_r, r_l, and gp_in and the bit xEQt1 can trigger an interrupt or enable simple polling techniques. See chapter 5.3, register 01 1110 for accessing the input bits. |
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