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TMC4210 Datasheet(PDF) 13 Page - TRINAMIC Motion Control GmbH & Co. KG. |
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TMC4210 Datasheet(HTML) 13 Page - TRINAMIC Motion Control GmbH & Co. KG. |
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13 / 48 page  TMC4210 DATASHEET (Rev. 1.03 / 2015-JUN-03) 13 www.trinamic.com tSD tSD CLK sdi_c_bit#31 tSCKCL tSCKCH tSUCSC tHDCSC 1 x SDI_C sampled one full 32 bit datagram SDO_C (for TMC429-I) SDI_C SCK_C nSCS_C sdi_c_bit#30 . . . sdi_c_bit#1 30 x sampled SDI_C sdi_c_bit#0 1 x SDI_C sampled tCLK tDATAGRAMuC tPD tIS tSD tSI tHDCSC tSUCSC sdo_c_bit#31 sdo_c_bit#30 ... sdo_c_bit#1 sdo_c_bit#0 nINT sdo_c_bit#31 sdo_c_bit#30 ... sdo_c_bit#1 sdo_c_bit#0 nINT SDOZ_C Figure 5.1 Timing diagram of the serial µC interface EXPLANATORY NOTES - While the data transmission from the microcontroller to the TMC4210 is idle, the low active serial chip select input nSCS_C and also the serial data clock signal SCK_C are set to high. - While the signal nSCS_C is high, the TMC4210 assigns the status of the internal low active interrupt signal nINT to the serial data output SDO_C. - The data signal SDI_C driven by the microcontroller has to be valid at the rising edge of the serial data clock input SCK_C. The maximum duration of the serial data clock period is unlimited. - While the µC interface of the TMC4210 is idle, the SDO_C signal is the (active low) interrupt status nINT of the integrated interrupt controller of the TMC4210. The timing of the multiplexed interrupt status signal nINT is characterized by the parameters t IS and tSI (see chapter 13.3). The following SPI clock frequencies are recommended in order to avoid possible issues concerning the SPI frequency between microcontroller and TMC4210: - For fCLK = 16MHz an upper SPI clock frequency of 1MHz is recommended. - For fCLK = 32MHz an upper SPI clock frequency of 2MHz is recommended. PROCEDURE OF DATA TRANSMISSION 1. The signal nSCS_C has to be high for at least three clock cycles before starting a datagram transmission. To initiate a transmission, the signal nSCS_C has to be set to low. 2. Three clock cycles later the serial data clock may go low. 3. The most significant bit (MSB) of a 32 bit wide datagram comes first and the least significant bit (LSB) is transmitted as the last one. 4. A data transmission is finished by setting nSCS_C high three or more CLK cycles after the last rising SCK_C slope. 5. So, nSCS_C and SCK_C change in opposite order from low to high at the end of a data transmission as these signals change from high to low at the beginning. In contrast to most other SPI compatible devices, the serial data output SDO_C of the TMC4210-I is always driven. It will never be high impedance Z. If high impedance is required for the SDO_C connected to the microcontroller, it can be realized using a single gate 74HCT1G125. |
Similar Part No. - TMC4210 |
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Similar Description - TMC4210 |
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