TMC424 Datasheet – (V1.04 / 2015-JUL-01)

12/21

Copyright © 2011 TRINAMIC Motion Control GmbH & Co. KG

5 Serial Peripheral Interface (SPI) with 32-bit Register

5.1 Description and Specification

Four pins named nSCS, SCK, SDI and SDO form the serial peripheral interface from a microcontroller to

the TMC424. The communication between the microcontroller and the TMC424 takes place via

datagrams with a fixed length of 32 bit. The microcontroller always acts as master and the TMC424 as

slave.

shifted with the rising edge of the clock signal SCK into the 32-bit register. The content of this register

is copied after 32-bits with the rising edge of the selection signal nSCS into a buffer register of 32-bit

processes serial data synchronously to the clock signal CLK.

Because of on-the-fly processing of the input data stream, the serial microcontroller interface of the

TMC424 requires the serial data clock signal SCK to have a minimum low / high time of three clock

cycles. The data signal SDI driven by the microcontroller has to be valid at the rising edge of the serial

data clock input SCK. The maximum duration of the serial data clock period is unlimited.

A complete serial datagram frame has a fixed length of 32 bit. While the data transmission from the

microcontroller to the TMC424 is idle, the low active serial chip select input nSCS and also the serial

data clock signal SCK are set to high. The serial data input SDI of the TMC429 has to be driven by the

microcontroller. Like other SPI compatible devices, the SDO signal of the TMC424 is high impedance ‘Z’

as long as nSCS is high.

The signal nSCS has to be high for at least three clock cycles before starting a datagram transmission.

To initiate a transmission, the signal nSCS has to be set to low. Three clock cycles later the serial data

clock may go low. The most significant bit (MSB) of a 32 bit wide datagram comes first and the least

significant bit (LSB) is transmitted as the last one. A data transmission is finished by setting nSCS high

for three or more CLK cycles after the last rising SCK slope. nSCS and SCK change in opposite order

from low to high at the end of a transmission as these signals change from high to low at the

beginning. The timing of the serial microcontroller interface is outlined here:

tSD

tSD

CLK

sdi_bit#31

tSCKCL

tSCKCH

tSUCSC

tHDCSC

1 x SDI_C sampled

one full 32 bit datagram

SDO

SDI

SCK

nSCS

sdi_bit#30 . . . sdi_bit#1

30 x sampled SDI_C

sdi_bit#0

1 x SDI_C sampled

tCLK

tDATAGRAMuC

sdo_bit#31

sdo_bit#30 ... sdo_bit#1

sdo_bit#0

tPD

tIS

tSD

tSI

tHDCSC

tSUCSC

Figure 7: Timing diagram of the Serial Interface