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4X16E83VTW-6 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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4X16E83VTW-6 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 9 page  4 the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ- MODIFY-WRITE occurs when WE falls after CAS# (CASL# or CASH#) is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFY- WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE Figure 2 WORD and BYTE READ Example STORED DATA 1 1 0 1 1 1 1 1 RAS# CASL# WE# Z = High-Z ADDRESS 1 ADDRESS 0 0 1 0 1 0 0 0 0 WORD READ LOWER BYTE READ STORED DATA 1 1 0 1 1 1 1 1 CASH# OUTPUT DATA 1 1 0 1 1 1 1 1 STORED DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z OUTPUT DATA 1 1 0 1 1 1 1 1 OUTPUT DATA 1 1 0 1 1 1 1 1 OUTPUT DATA 1 1 0 1 1 1 1 1 STORED DATA 1 1 0 1 1 1 1 1 UPPER BYTE (DQ8-DQ15) OF WORD LOWER BYTE (DQ0-DQ7) OF WORD 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 64Mb EDO DRAM offers an accelerated page mode cycle by elimi- nating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates like any DRAM READ or FAST-PAGE- MODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are DRAM ACCESS (continued) 4 MEG x 16 EDO DRAM |
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