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TPS65010RGZT Datasheet(PDF) 25 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 63 page  TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 voltage drops below this threshold, the TPS65010 sets the PWRFAIL pin low and after a time t(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65010 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t(overtemp). The TPS65010 automatically restarts when the UVLO (or overtemperature) condition is no longer present. The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins. 7.3.5 Power-Up Sequencing The TPS65010 power-up sequencing is designed to allow the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in Table 3: Table 3. Control Pins INPUT OR PIN NAME FUNCTION OUTPUT PS_SEQ I Input signal indicating power up and down sequence of the switching converters. PS_SEQ = 0 forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up first and down last. DEFCORE I Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V, DEFCORE = VCC defaults VCORE to 1.6 V. DEFMAIN I Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3.0 V, DEFMAIN = VCC defaults VMAIN to 3.3 V. LOW_PWR I The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the processor is in deep sleep mode. Alternatively VCORE can be disabled in low-power mode if the LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in the VDCDC1 register. The TPS65010 uses the rising edge of the internal signal formed by a logical AND of LOW_PWR and ENABLE LP to enter low-power mode. TPS65010 is forced out of low-power mode by de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating the HOT_RESET pin. There are two ways to get the device back into low-power mode: a) toggle the LOW_PWR pin, or b) toggle the low-power bit when the LOW_PWR pin is held high. PB_ONOFF I PB_ONOFF can be used to exit the low-power mode and return the core voltage to the value before low-power mode was entered. If PB_ONOFF is used to exit the low-power mode, then the low-power mode can be reentered by toggling the LOW_PWR pin or by toggling the low power bit when the LOW_PWR pin is held high. A 1-M Ω pulldown resistor is integrated in TPS65010. PB_ONOFF is internally de-bounced by the TPS65010. A maskable interrupt is generated when PB_ONOFF is activated. HOT_RESET I The HOT_RESET pin has a very similar functionality to the PB_ONOFF pin. In addition it generates a reset (MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any TPS65010 settings unless low-powermode was active in which case it is exited. A 1-M Ω pullup resistor to VCC is integrated in TPS65010. HOT_RESET is internally de-bounced by the TPS65010. BATT_COVER I The BATT_COVER pin is used as an early warning that the main battery is about to be removed. BATT_COVER = VCC indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not in place. TPS65010 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is also held low when BATT_COVER goes low. This feature may be disabled, by tying BATT_COVER permanently to VCC. The TPS65010 shuts down the main and the core converters, and sets the LDOs into low-powermode. A 2-M Ω pulldown resistor is integrated in the TPS65010 at the BATT_COVER pin. BATT_COVER is internally de-bounced by the TPS65010. RESPWRON O RESPWRON is held low while the switching converters (and any LDO's defined as default on) are starting up. It is determined by the state of LDO1's output voltage; when this is good then RESPWRON is high, when VLDO1 is low then RESPWRON is low. RESPWRON is held low for tn(RESPWRON) sec after VLDO1 has settled. MPU_RESET O MPU_RESET can be used to reset the processor if the user activates theHOT_RESET button. The MPU_RESET output is active for t(MPU_nRESET) sec. It also forces TPS65010 to leave low- powermode. MPU_RESET is also held low as long as RESPWRON is held low. PWRFAIL O PWRFAIL indicates when VCC < V(UVLO), when the TPS65010 is about to shut down due to an internal overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as RESPWRON is held low. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TPS65010 |
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