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TPS65010RGZT Datasheet(PDF) 12 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 12 Page - Texas Instruments |
12 / 63 page ![]() TPS65010 SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 www.ti.com 6.8 Dissipation Ratings See (1). AMBIENT TEMPERATURE MAX POWER DISSIPATION FOR Tj= 125°C (2) DERATING FACTOR ABOVE TA = 55°C 25°C 3 W 30 mW/°C 55°C 2.1 W 30 mW/°C (1) The TPS65010 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7 mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k board. (2) Consideration needs to be given to the maximum charge current when the assembled application board exhibits a thermal impedance which differs significantly from the JEDEC high-k board. 6.9 Typical Characteristics Table 1. Table of Graphs FIGURE Figure 1, Figure 2, Efficiency vs Output current Figure 3, Figure 4 Quiescent current vs Input voltage Figure 5 Switching frequency vs Temperature Figure 6 Figure 7, Output voltage vs Output current Figure 8 LDO1 Output voltage vs Output current Figure 9 LDO2 Output voltage vs Output current Figure 10 Line transient response (main) Figure 11 Line transient response (core) Figure 12 Line transient response (LDO1) Figure 13 Line transient response (LDO2) Figure 14 Load transient response (main) Figure 15 Load transient response (core) Figure 16 Load transient response (LDO1) Figure 17 Load transient response (LDO2) Figure 18 Output Voltage Ripple (PFM) Figure 19 Output Voltage Ripple (PWM) Figure 20 Startup timing Figure 21 Figure 22, Dropout voltage vs Output current Figure 23 PSRR (LDO1 and LDO2) vs Frequency Figure 24 12 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: TPS65010 |
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