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TPS65010RGZT Datasheet(PDF) 53 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 53 Page - Texas Instruments |
53 / 63 page ![]() TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 9 Power Supply Recommendations 9.1 LDO1 Output Voltage Adjustment The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must not exceed 1 M Ω to minimize voltage changes due to leakage current into the feedback pin. The output voltage for LDO1 after start up is the voltage set by the external resistor divider. It can be reprogrammed with the I2C interface to the three other values defined in the register VREGS1. 10 Layout 10.1 Layout Guidelines The input capacitors for the DC-DC converters must be placed as close as possible to the VINMAIN, VINCORE, and VCC pins. • The inductor of the output filter must be placed as close as possible to the device to provide the shortest switch node possible, reducing the noise emitted into the system and increasing the efficiency. • Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy. Feedback must be routed away from noisy sources such as the inductor. If possible, route on the opposite side from the switch node and inductor. Use a GND plane or keep out region to isolate the feedback trace from noisy sources. • Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This will ensure best regulation at the feedback point. • Place the device as close as possible to the most demanding or sensitive load. The output capacitors must be placed close to the input of the load. This will ensure the best AC performance possible. • The input and output capacitors for the LDOs must be placed close to the device for best regulation performance. • Use vias to connect thermal pad to ground plane. • TI recommends using the common ground plane for the layout of this device. The AGND can be separated from the PGND, but a large low parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections. If the AGND and PGND planes are separated, have one connection point to reference the grounds together. Place this connection point close to the IC. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 53 Product Folder Links: TPS65010 |
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