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TPS65010RGZT Datasheet(PDF) 45 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 63 page  TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 Table 26. LDO1 Enable and LDO1 OFF/nSLP Functions (continued) LDO1 ENABLE LDO1 OFF / nSLP LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE 1 0 ON, full power ON, reduced power / performance 1 1 ON, full power OFF Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed through the serial interface. Table 27. LDO1 Settings LDO11 LDO10 VLDO1 0 0 ADJ 0 1 2.5 V 1 0 2.75 V 1 1 3.0 V 7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h) MASK3 Register MASK3 B7 B6 B5 B4 B3 B2 B1 B0 Edge trigger Edge trigger Edge trigger Edge trigger Bit name Mask GPIO4 Mask GPIO3 Mask GPIO2 Mask GPIO1 GPIO4 GPIO3 GPIO2 GPIO1 Default 0 0 0 0 0 0 0 0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W The MASK3 register must be considered when any of the GPIO pins are programmed as inputs. Bit 7-Bit 4 - Edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or a falling edge. • 0 = falling edge triggered. • 1 = rising edge triggered. Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (MASK3<0:3> =0). 7.6.16 DEFGPIO Register Address: (10h—Reset: 00h) Table 28. DEFGPIO Register DEFGPIO B7 B6 B5 B4 B3 B2 B1 B0 Bit name IO4 IO3 IO2 IO1 Value GPIO4 Value GPIO3 Value GPIO2 Value GPIO1 Default 0 0 0 0 0 0 0 0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W The DEFGPIO register is used to define the GPIO pins to be either input or output. Bit 7-Bit 4 - IO<4:1>: • 0 = sets the corresponding GPIO to be an input. • 1 = sets the corresponding GPIO to be an output. Bit 3-Bit 0 - Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by the corresponding bit. The output circuit for each GPIO is an open-drain NMOS requiring an external pullup resistor. • 1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin. • 0 = turns the open-drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to which the pullup resistor is connected. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Links: TPS65010 |
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