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TPS65010RGZT Datasheet(PDF) 43 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 43 Page - Texas Instruments |
43 / 63 page ![]() TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 Table 20. UVLO Settings (continued) UVLO1 UVLO0 VUVLO 1 1 3.25 V (reset) Bit 4 - ENABLE SUPPLY: • 0 = not allowed • 1 = must be left set. Bit 3 - ENABLE LP: • 0 = disables the low-powerfunction of the LOW_PWR pin. • 1 = enables the low-powerfunction of the LOW_PWR pin. Bit 2 - MAIN DISCHARGE: • 0 = disable the active discharge of the VMAIN converter output. • 1 = enable the active discharge of the VMAIN converter output, when the converter is disabled. Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to Table 21, with the rest in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written through the serial interface after start-up. Table 21. MAIN Settings MAIN1 MAIN0 VMAIN 0 0 2.5 V 0 1 2.75 V 1 0 3.0 V 1 1 3.3 V 7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h) Table 22. VDCDC2 Register VDCDC2 B7 B6 B5 B4 B3 B2 B1 B0 CORE Bit name LP_COREOFF CORE2 CORE1 CORE0 CORELP1 CORELP0 VIB DISCHARGE Default 0 1 1 DEFCORE 1 0 0 0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.6 V. The reset is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.6 V. Bit 7 - LP_COREOFF: • 0 = VCORE converter is enabled in low-powermode. • 1 = VCORE converter is disabled in low-powermode. Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The reset can subsequently be overwritten through the serial interface after start-up. Table 23. CORE Settings CORE2 CORE1 CORE0 VCORE 0 0 0 0.85 V 0 0 1 1.0 V 0 1 0 1.1 V 0 1 1 1.2 V 1 0 0 1.3 V 1 0 1 1.4 V 1 1 0 1.5 V Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: TPS65010 |
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