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TPS65010RGZT Datasheet(PDF) 42 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 63 page  TPS65010 SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 www.ti.com Table 16. LED2_ON Register (continued) LED2_ON B7 B6 B5 B4 B3 B2 B1 B0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output. Bit 7 LED21: Control is determined by LED21 and LED22 according to Table 17. Bit 6-Bit 0 - LED2_PER<6:0> are used to program the ON-time of the open-drain output transistor at the LED2 pin. The minimum ON-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the ON-time. 7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h) Table 17. LED2_PER LED2_PER B7 B6 B5 B4 B3 B2 B1 B0 Bit name LED22 LED2 PER6 LED2 PER5 LED2 PER4 LED2 PER3 LED2 PER2 LED2 PER1 LED2 PER 0 Default 0 0 0 0 0 0 0 0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 LED22: Control is determined by LED21 and LED22 according to Table 17. Bit 6-Bit 0 - LED2_ON<6:0> are used to program the time period of the open-drain output transistor at the LED2 pin. The minimum ON-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the ON- time. Table 18. LED2 Open-Drain Output Setting LED21 LED22 BEHAVIOR OF LED2 OPEN-DRAIN OUTPUT 0 0 Off (default) 0 1 Blink 1 0 Off 1 1 Always On 7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h) Table 19. VDCDC1 Register VDCDC1 B7 B6 B5 B4 B3 B2 B1 B0 Bit name FPWM UVLO1 UVLO0 ENABLE ENABLE MAIN MAIN1 MAIN0 SUPPLY LP DISCHARGE Default 0 1 1 1 0 0 1 DEFMAIN Read/write R/W R/W R/W R/W R/W R/W R/W R/W The VDCDC1 register is used to program the VMAIN switching converter. Bit 7 - FPWM: forced PWM mode for DC-DC converters. • 0 = MAIN and the CORE DC-DC converter are allowed to switch into PFM mode. • 1 = MAIN and the CORE DC-DC converter operate with forced fixed frequency PWM mode and are not allowed to switch into PFM mode at light load. Bit 6-Bit 5 - UVLO<1:0>: The under-voltage threshold voltage is set by UVLO1 and UVLO0 according to the Table 20. Table 20. UVLO Settings UVLO1 UVLO0 VUVLO 0 0 2.5 V 0 1 2.75 V 1 0 3.0 V 42 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: TPS65010 |
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