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TPS65010RGZT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 63 page ![]() TPS65010 SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. PGND2 46 — Power ground for VCORE converter. Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This VCC 6 I must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies serial interface block. VCORE 48 I VCORE feedback voltage sense input, connect directly to VCORE. VINCORE I Input voltage for VCORE step-down converter. This must be connected to the same voltage 5 supply as VINMAIN and VCC. VINMAIN_A, 7,8 I Input voltage for VMAIN step-down converter. This must be connected to the same voltage VINMAIN_B supply as VINCORE and VCC. VMAIN 13 I VMAIN feedback voltage sense input, connect directly to VMAIN LDO REGULATOR SECTION AGND1 21 — Analogue ground connection. All analog ground pins are connected internally on the chip. VFB_LDO1 23 I Feedback input from external resistive divider for LDO1. VINLDO1 22 I Input voltage for LDO1. VINLDO2 19 I Input voltage for LDO2. VLDO1 24 O Output voltage for LDO1. VLDO2 20 O Output and feedback voltage for LDO2. DRIVER SECTION LED2 2 O LED driver, with blink rate programmable through serial interface. VIB 3 O Vibrator driver, enabled through serial interface. CONTROL AND I2C SECTION BATT_COVER 39 I Indicates if battery cover is in place. DEFCORE 1 I Input signal indicating default VCORE voltage, 0 = 1.5 V, 1 = 1.6 V. DEFMAIN 12 I Input signal indicating default VMAIN voltage, 0 = 3.0 V, 1 = 3.3 V. GPIO1 26 I/O General-purpose open-drain input/output. GPIO2 25 I/O General-purpose open-drain input/output. GPIO3 18 I/O General-purpose open-drain input/output. GPIO4 17 I/O General-purpose open-drain input/output. HOT_RESET 31 I Push button reset input used to reboot or wake-up processor through TPS65010. IFLSB 28 I LSB of serial interface address used to distinguish two devices with the same address. INT O Indicates a charge fault or termination, or if any of the regulator outputs are below the lower 35 tolerance level, active low (open-drain). LOW_PWR 36 I Input signal indicating deep sleep mode, VCORE is lowered to predefined value or disabled. MPU_RESET 32 O Open-drain reset output generated by user activated HOT_RESET PB_ONOFF 47 I Push button enable pin, also used to wake-up processor from low power mode. PS_SEQ 14 I Sets power-up/down sequence of step-down converters. PWRFAIL O Open-drain output. Active low when UVLO comparator indicates low VBAT condition or 34 when shutdown is about to occur due to an overtemperature condition or when the battery cover is removed (BATT_COVER has gone low). RESPWRON 33 O Open-drain system reset output, generated according to the state of the LDO1 output voltage. SCLK 30 I Serial interface clock line. SDAT 29 I/O Serial interface data/address. 4 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: TPS65010 |
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