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TPS65010RGZT Datasheet(PDF) 36 Page - Texas Instruments

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Part # TPS65010RGZT
Description  Power and Battery Management IC for Li-Ion Powered Systems
Download  63 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65010RGZT Datasheet(HTML) 36 Page - Texas Instruments

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...
SCLK
SDAT
A6
R6
R5
R0
ACK
D7
D6
D5
D0
ACK
R7
ACK
R/W
A0
A4
A5
0
0
0
0
Stop
Start
Slave Address
Register Address
Data
...
...
...
...
...
S
P
START Condition
STOP Condition
CE
DATA
CLK
Data Line
Stable
Data Valid
Change
of Data
Allowed
DATA
CLK
TPS65010
SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015
www.ti.com
Programming (continued)
7.5.3 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65010 has a 7-bit address with the
LSB set by the IFLSB pin, this allows the connection of two devices with the same address to the same bus. The
6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh
being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65010 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65010 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65010 device must leave the data line high to enable the master to generate the stop
condition.
Figure 36. Bit Transfer on the Serial Interface
Figure 37. START and STOP Conditions
NOTE: SLAVE = TPS65010
Figure 38. Serial Interface WRITE to TPS65010 Device
36
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Product Folder Links: TPS65010


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