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TPS65010RGZT Datasheet(PDF) 34 Page - Texas Instruments

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Part # TPS65010RGZT
Description  Power and Battery Management IC for Li-Ion Powered Systems
Download  63 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65010RGZT Datasheet(HTML) 34 Page - Texas Instruments

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VCORE
VMAIN
VLDO1
VLDO2
95% VCORE
95% VLDO2
HOT_RESET
HOT_RESET
DEGLITCH
INT
MPU_RESET
tGLITCH
t(MPU_RESET)
TPS65010
SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015
www.ti.com
Figure 35. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management for INT
Behavior)
7.5 Programming
7.5.1 LED2 Output
The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off.
The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum
blink ON-time is 10 ms and this can be increased in 127 10 ms-steps to 1280 ms. For both PG and LED2, the
minimum blink period is 100 ms and this can be increased in 127 100-ms steps to 12800 ms.
7.5.2 Interrupt Management
The open-drain INT pin is used to combine and report all possible conditions through a single pin. Battery and
chip temperature faults, precharge timeout, charge timeout, taper timeout and termination current are each
capable of setting INT low, i.e. active. INT can also be activated if any of the regulators are below the regulation
threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can
be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to
mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2
or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS,
REGSTATUS and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are
acknowledged by reading these registers. If a 1 is present in any location then the TPS65010 automatically sets
the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register
contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor
should not normally need to access the ACKINT1 or ACKINT2 registers.
34
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Product Folder Links: TPS65010


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