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TPS65010RGZT Datasheet(PDF) 23 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 63 page  ( ) I(min) O(max) O(max) DS(on)max L V V I r R = + ´ + PFM Mode at Light Load Comp High Comp Low Comp Low 2 PFM Mode at Medium to Full Load 1.6% 0.8% VO TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 During the power save mode the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal Vout, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current then the output voltage rises until the comp high threshold is reached, typically 1.6% above the nominal Vout, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp low 2 threshold), whereupon power save mode is exited and the converter returns to PWM mode. These control methods reduce the quiescent current to typically to 12-µA per converter and the switching frequency to a minimum achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. Refer to Figure 28 for detailed operation of the power save mode. The power save mode can be disabled through the I2C interface to force the converters to stay in fixed frequency PWM mode. Figure 28. Power Save Mode Thresholds and Dynamic Voltage Positioning 7.3.2.2 Forced PWM The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is used to minimize ripple on the output voltages. 7.3.2.3 Dynamic Voltage Positioning As described in the power save mode operation sections and as detailed in Figure 13, the output voltage is typically 1.2% above the nominal output voltage at light load currents as the device is in power save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. During a load transient from full load to light load the voltage overshoot is also minimized due to active regulation turning on the N-channel rectifier switch. 7.3.2.4 Soft Start Both converters have an internal soft start circuit that limits the inrush current during start-up. The soft start is implemented as a digital circuit increasing the switch current in 4 steps up to the typical maximum switch current limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor and load current. 7.3.2.5 100% Duty Cycle Low Dropout Operation The TPS65010 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. i.e., The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated as: Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS65010 |
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