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TPS65010RGZT Datasheet(PDF) 22 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 63 page  I(MAIN) I(CORE) (skipmain) (skipcore) V V I I 17 42 = = W W TPS65010 SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) Table 2. Thermal Considerations for Setting Charge Current AMBIENT TEMPERATURE MAX POWER DISSIPATION FOR Tj= 125°C DERATING FACTOR ABOVE TA = 55°C 25°C 3 W 30 mW/°C 55°C 2.1 W Consideration needs to be given to the maximum charge current when the assembled application board exhibits a thermal impedance, which differs significantly from the JEDEC high-k board. The charger has a thermal shutdown feature, which suspends charging if the TPS65010 junction temperature rises above a threshold of 145°C. This threshold is set 15°C below the threshold used to power down the TPS65010 completely. 7.3.2 Step-Down Converters, VMAIN and VCORE The TPS65010 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA. The converter output voltages are programmed through the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3.0-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground the default is 3.0 V, if it is tied to VCCthe default is 3.3 V. The core converter defaults to either 1.5 V or 1.6 V depending on whether the DEFCORE configuration pin is tied to GND or to VCC respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up through the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register. The step-down converter outputs (when enabled) are monitored by power good comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled. During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N- channel rectifier and turning on the P-channel switch. The error amplifier, together with the input voltage, determines the rise time of the saw tooth generator, and therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a very good line and load transient regulation. The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turn on and the CORE switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V 7.3.2.1 Power Save Mode Operation As the load current decreases, the converter enters the power save mode operation. During power save mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then power save mode is entered. The typical threshold can be calculated as follows: (1) 22 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: TPS65010 |
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