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TPS65010RGZT Datasheet(PDF) 21 Page - Texas Instruments |
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TPS65010RGZT Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 63 page  TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.1.5 Battery Voltage Regulation The voltage regulation feedback is through the VBAT pin. This pin is tied directly to the positive side of the battery pack. The TPS65010 monitors the battery-pack voltage between the VBAT and AGND pins. The TPS65010 is offered in a fixed-voltage version of 4.2 V. As a safety backup, the TPS65010 also monitors the charge time in the fast-charge mode. If taper current is not detected within this time period, t(CHG), the TPS65010 turns off the charger and indicates FAULT in the CHGSTATUS register. In the case of a FAULT condition, the TPS65010 reduces the current to I(DETECT). I(DETECT) is used to detect a battery replacement condition. Fault condition is cleared by POR through the serial interface. Note that the safety timer is reset if the TPS65010 is forced out of the voltage regulation mode. The fast-charge timer is disabled by default to allow charging during normal operation of the end equipment. It is enabled through the CHGCONFIG register. 7.3.1.6 Charge Termination and Recharge The TPS65010 monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER), is detected the TPS65010 initiates the taper timer, t(TAPER). Charge is terminated after the timer expires. The TPS65010 resets the taper timer in the event that the charge current returns above the taper threshold, I(TAPER). After a charge termination, the TPS65010 restarts the charge once the voltage on the VBAT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. The fast charge timer and the taper timer must be enabled by programming CHGCONFIG(5)=1. A thermal suspend will suspend the fast charge and taper timers. In addition to the taper current detection, the TPS65010 terminates charge in the event that the charge current falls below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition. When a full battery is replaced with an empty battery, the TPS65010 detects that the VBAT voltage is below the recharge threshold and starts charging the new battery. The taper and termination bits are cleared in the CHGSTATUS register and if the INT pin is still active due to these two interrupt sources, then it is de-asserted. Depending on the transient seen at the VCC pin, all registers may be set to their default values and require reprogramming with any nondefault values required, such as enabling the fast charge timer and taper termination; this must only happen if VCC drops below approximately 2 V. 7.3.1.7 Sleep Mode The TPS65010 charger enters the low-power sleep mode if both input sources are removed from the circuit. This feature prevents draining the battery during the absence of input power. 7.3.1.8 PG Output The open-drain power good (PG) output indicates when a valid power supply is present for the charger. This can be either from the AC adapter input or from the USB. The output turns ON when a valid voltage is detected. A valid voltage is detected whenever the voltage on either pin AC or pin USB rises above the voltage on VBAT plus 100 mV. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. A voltage greater than the V(CHGOVLO) threshold (typ 6.6 V) at the AC input is not valid and does not activate the PG output. The PG output is held in high impedance state if the charger is in reset by programming CHGCONFIG(6)=1. The PG output can also be programmed through the LED1_ON and LED1_PER registers in the serial interface. It can then be programmed to be permanently on, off, or to blink with defined ON-times and period-times. PG is controlled per default through the charger. 7.3.1.9 Thermal Considerations for Setting Charge Current The TPS65010 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7 mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k board with zero air flow. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPS65010 |
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