TPS61193

SNVSAF4 – OCTOBER 2015

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10 Layout

10.1 Layout Guidelines

Figure 26 is a layout recommendation for TPS61193 used to demonstrate the principles of a good layout. This

layout can be adapted to the actual application layout if or where possible. It is important that all boost

components are close to the chip, and the high current traces must be wide enough. By placing boost

components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This

way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor should

as close to the device as possible.

Here are some main points to help the PCB layout work:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close as

possible to the SW and PGND pins. Input and output capacitor grounds need to be close to each other to

minimize current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents try to find route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the “positive” current route in the ground plane, if the ground plane is intact

under the route.

•

The GND plane needs to be intact under the high current boost traces to provide shortest possible return path

and smallest possible current loops for high frequencies.

•

Current loops when the boost switch is conducting and not conducting need to be on the same direction in

optimal case.

•

Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating

inductor 180° changes current direction.

•

Use separate power and noise-free grounds. Power ground is used for boost converter return current and

noise-free ground for more sensitive signals, like LDO bypass capacitor grounding as well as grounding the

GND pin of the device itself.

•

Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the

diode cathode.

•

Place LDO 1-µF bypass capacitor as close to the LDO pin as possible.

•

Input and output capacitors need strong grounding (wide traces, many vias to GND plane).

•

If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.

•

Output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to

become unstable on some loads, and this increases EMI. DC-bias characteristics need to be obtained from

the component manufacturer; it is not taken into account on component tolerance. X5R/X7R capacitors are

recommended.

26

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