TPS61193

SNVSAF4 – OCTOBER 2015

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8.2.2.1 Design Requirements

DESIGN PARAMETER

VALUE

4.5…30 V

LED string

3P2S LEDs (7.2 V)

LED string current

100 mA

Maxmum output voltage

10 V

SEPIC switching frequency

2.2 MHz

External sync for SEPIC

used

Spread spectrum

Internal spread spectrum disabled (external sync used)

L1, L2

10 µH

10 µF 50 V

2 × (10 µF 50-V ceramic) + 33 µF 50-V electrolytic

C1

10 µF 50V ceramic

2 × (10 µF 50-V ceramic) + 33 µF 50-V electrolytic

1 µF 10-V

24 k

Ω

24 k

Ω

R1

184 k

Ω

R2

130 k

Ω

R3

10 k

Ω

8.2.2.2 Detailed Design Procedure

In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output

voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See Detailed

Design Procedure for general external component guidelines. Main differences of SEPIC compared to boost are

described below.

Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstage-

designer. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing

DC/DC Converters Based on SEPIC Topology (SLYT309).

8.2.2.2.1

Inductor

In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the

input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or

using equations in SLYT309.

8.2.2.2.2

Diode

In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak

repetitive current should be greater than SW pin current limit (up to 3 A for transients) to ensure reliable

operation in boost mode. Average current rating should be greater than the maximum output current. Diode

voltage rating must be higher than sum of input and output voltages.

8.2.2.2.3

Capacitor C1

Ceramic capacitor with low ESR is recommended. Diode voltage rating must be higher than maximum input

voltage.

24

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