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LP8862-Q1

SNVSA75A – NOVEMBER 2015 – REVISED NOVEMBER 2015

www.ti.com

8.2.2.1 Detailed Design Procedure

In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output

voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See Detailed

Design Procedure for general external component guidelines. The main differences of SEPIC compared to boost

are described below.

Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstage-

designer. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing

DC/DC Converters Based on SEPIC Topology (SLYT309).

8.2.2.1.1

Inductor

In SEPIC mode, coupled coil saturation rating should be higher than input side inductor peak current. Current

values can be estimated using Power Stage Designer™ Tool or using equations in SLYT309.

8.2.2.1.2

Diode

In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak

repetitive current must be greater than SW pin current limit (up to 3 A for transients) to ensure reliable operation.

Average current rating must be greater than the maximum output current. Voltage rating must be higher than

sum of input and output voltages.

8.2.2.1.3

Capacitor C1

A ceramic capacitor with low ESR is recommended. Voltage rating must be higher than maximum input voltage.

8.2.2.2 Application Curves

Two strings, 2 LEDs per string

160 mA/string

Figure 25. SEPIC Efficiency

26

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