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TPS65022 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS65022 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 47 page TPS65022 www.ti.com SLVS667B – JULY 2006 – REVISED JANUARY 2016 Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Fixed output voltage All VDCDC3 VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 800 mA –2% 2% FPWMDCDC3 = 0 Fixed output voltage All VDCDC3 VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 800 mA –1% 1% FPWMDCDC3 = 1 Adjustable output voltage with resistor divider at VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; –2% 2% DEFDCDC3 FPWMDCDC3 = 0 0 mA ≤ IO ≤ 800 mA Adjustable output voltage with resistor divider at VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; –1% 1% DEFDCDC3; FPWMDCDC3 = 1 0 mA ≤ IO ≤ 800 mA VINDCDC3 = VDCDC3 + 0.3 V (min 2.5 V) to 6 V; Line Regulation 0 %/V IO = 10 mA Load Regulation IO = 10 mA to 400 mA 0.25 %/A Soft start ramp time VDCDC3 ramping from 5% to 95% of target value 750 μs Internal resistance from L3 to GND 1 M Ω VDCDC3 discharge resistance DCDC3 discharge =1 300 Ω VLDO1 and VLDO2 LOW DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V VO LDO2 output voltage range 1 3.3 V VI = 1.8 V, VO = 1.3 V 200 mA IO Maximum output current for LDO1, LDO2 VI = 1.5 V, VO = 1.3 V 120 I(SC) LDO1 and LDO2 short circuit current limit V(LDO1) = GND, V(LDO2) = GND 400 mA IO = 50 mA, VINLDO = 1.8 V 120 mV Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.5 V 65 150 IO = 200 mA, VINLDO = 1.8 V 300 Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1% VINLDO1,2 = VLDO1,2 + 0.5 V Line regulation for LDO1, LDO2 –1% 1% (min 2.5 V) to 6.5 V, IO = 10 mA Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC V VIL Low level input voltage 0 0.1 V Input bias current 0.001 0.05 μA THERMAL SHUTDOWN T(SD) Thermal shutdown Increasing junction temperature 160 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDERVOLTAGE LOCK OUT UVLO Internal UVLO VCC falling –2% 2.35 2% V V(UVLO_HYST) Internal UVLO comparator hysteresis 120 mV VOLTAGE DETECTOR COMPARATORS Comparator threshold (PWRFAIL_SNS, Falling threshold –1% 1 1% V LOWBAT_SNS) Hysteresis 40 50 60 mV Propagation delay 25 mV overdrive 10 μs POWER GOOD VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, V(PGOODF) –12% –10% –8% decreasing VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, V(PGOODR) –7% –5% –3% increasing Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS65022 |
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