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TPS65022 Datasheet(PDF) 38 Page - Texas Instruments |
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TPS65022 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 47 page  L3 PGND3 VDCDC3 VIN TPS65022 SLVS667B – JULY 2006 – REVISED JANUARY 2016 www.ti.com 9 Power Supply Recommendations For a supply voltage on pins VCC, VINDCDC1, VINDCDC2 and VINDCDC3 below 3 V, TI recommends enabling the DCDC1, DCDC2 and DCDC3 converters in sequence. If all 3 step-down converters are enabled at the same time while the supply voltage is close to the internal reset detection threshold, a reset may be generated during power-up. Therefore TI recommends enabling the DC-DC converter in sequence. This can be done by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltage of one of the other step-down converters. If a voltage above 3 V is applied on pin VBACKUP while VCC and VINDCDCx is below 3 V, there is no restriction in the power-up sequencing as VBACKUP will be used to power the internal circuitry. 10 Layout 10.1 Layout Guidelines As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues as well as EMI problems. It is critical to provide a low impedance ground path. Use wide and short traces for the main current paths. The input capacitors should be placed as close as possible to the IC pins as well as the inductor and output capacitor. For TPS65022, connect the PGND pins of the device to the PowerPAD™ land of the PCB and connect the analog ground connections (AGND) to the PGND at the PowerPAD. It is essential to provide a good thermal and electrical connection of all GND pins using multiple vias to the GND-plane. Keep the common path to the AGND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx line should be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, and L3 traces). 10.2 Layout Example Figure 40. DC–DC Regulator Layout Example 38 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS65022 |
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