 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TPS65022 Datasheet(PDF) 36 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TPS65022 Datasheet(HTML) 36 Page - Texas Instruments |
|
|
36 / 47 page  t =2 (reset) x128x (1V-0.25V)xC(reset) 2 A m () VOUT DEFDCDCx =V x R1+R2 R2 R1=R2x VOUT VDEFDCDCx -R2 () VDCDC3 DCDC3_EN DEFDCDC3 AGND PGND L3 R1 R2 VO L CO VCC VINDCDC3 CI 1 F m 10R V(bat) TPS65022 SLVS667B – JULY 2006 – REVISED JANUARY 2016 www.ti.com Using an external resistor divider at DEFDCDCx: Figure 36. External Resistor Divider When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1 + R2) of the voltage divider should be kept in the 1-MR range in order to maintain a high efficiency at light load. V(DEFDCDCx) = 0.6 V (8) 8.2.2.5 VRTC Output The VRTC output is typically connected to the Vcc_Batt pin of a Intel® PXA270 processor. During power-up of the processor, the TPS65022 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 28).It is required that a 4.7- μF (minimum) capacitor be added to the VRTC pin even if the output is not used. 8.2.2.6 LDO1 and LDO2 The LDOs in the TPS65022 are general-purpose LDOs which are stable using ceramics capacitors. The minimum output capacitor required is 2.2 μF. The LDOs output voltage can be changed to different voltages between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from PXA270. The supply voltage for the LDOs must connect to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest efficiency. 8.2.2.7 TRESPWRON This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms. While there is no real upper and lower limit for the capacitor connected to TRESPWRON, do not leave signal pins open. where • t(reset) is the reset delay time • C(reset) is the capacitor connected to the TRESPWRON pin (9) The minimum and maximum values for the timing parameters called ICONST (2 µA), TRESPWRON_UPTH (1 V) and TRESPWRON_LOWTH (0.25 V) can be found under the electrical characteristics. 36 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS65022 |
Similar Part No. - TPS65022_16 |
|
Similar Description - TPS65022_16 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
