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TPS65022 Datasheet(PDF) 29 Page - Texas Instruments |
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TPS65022 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 47 page  TPS65022 www.ti.com SLVS667B – JULY 2006 – REVISED JANUARY 2016 7.6.6 CON_CTRL2 Register Address: 05h (read/write) Default Value: 40h Table 10. CON_CTRL2 Register CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 B0 Bit name and Core adj DCDC2 DCDC1 DCDC3 GO function allowed discharge discharge discharge Default 0 1 0 0 0 0 0 0 Default value UVLO + RESET(1) UVLO UVLO UVLO loaded by: DONE Read/Write R/W R/W R/W R/W R/W The CON_CTRL2 register can be used to take control the inductive converters. RESET(1): CON_CTRL2[6] is reset to its default value by one of these events: • undervoltage lockout (UVLO) • DCDC1_EN and DCDC3_EN pulled low • HOT_RESET pulled low • RESPWRON active • VRTC below threshold Bit 7 GO: 0 = no change in the output voltage for the DCDC3 converter 1 = the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage. Bit 6 CORE ADJ Allowed: 0 = the output voltage is set with the I2C register 1 = DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up. the output capacitor of the associated converter is not actively discharged when the converter is Bit 2– 0 0 = disabled 1 = the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load. 7.6.7 DEFCORE Register Address: 06h (read/write) Default Value: 14h/1Eh Table 11. DEFCORE Register DEFCORE B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function CORE4 CORE3 CORE2 CORE1 CORE0 Default 0 0 0 1 DEFDCDC3 1 DEFDCDC3 0 Default value loaded by: RESET(2) RESET(1) RESET(1) RESET(1) RESET(2) Read/Write R/W R/W R/W R/W R/W RESET(1): DEFCORE[3:1] are reset to the default RESET(2): DEFCORE[4] and DEFCORE[0] are reset value by one of these events: to the default value by one of these events: • undervoltage lockout (UVLO) • undervoltage lockout (UVLO) • DCDC1_EN and DCDC3_EN pulled low • DCDC1_EN pulled low • HOT_RESET pulled low • HOT_RESET pulled low • RESPWRON active • RESPWRON active • VRTC below threshold • VRTC below threshold Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: TPS65022 |
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Similar Description - TPS65022_16 |
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