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TPS65022 Datasheet(PDF) 23 Page - Texas Instruments |
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TPS65022 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 47 page  TPS65022 www.ti.com SLVS667B – JULY 2006 – REVISED JANUARY 2016 The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before VDCDC1 was disabled. 7.3.12.1 DEFLDO1 and DEFLDO2 These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of both LDOs can be changed during operation with the I2C interface as described in the interface description. Table 3. LDO1 and LDO2 Default Voltage Options DEFLDO2 DEFLDO1 VLDO1 VLDO2 0 0 1.1 V 1.3 V 0 1 1.5 V 1.3 V 1 0 2.6 V 2.8 V 1 1 3.15 V 3.3 V 7.3.12.2 Interrupt Management and the INT Pin The INT pin combines the outputs of the PGOOD comparators from each DC-DC converter and LDOs. The INT pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register is read through the serial interface, any active bits are then blocked from the INT output pin. Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts since this provides the POWER_OK function. 7.4 Device Functional Modes The TPS650231 device is in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold, 2.35 V (typically). Once the voltage at V CC has increased above UVLO, the device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use. 7.5 Programming 7.5.1 Serial Interface The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65022 has a 7-bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65022 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65022 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65022 device must leave the data line high to enable the master to generate the stop condition. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS65022 |
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