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TPS65022 Datasheet(PDF) 17 Page - Texas Instruments |
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TPS65022 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 47 page  DCDC2 STEP-DOWN CONVERTER SerialInterface SCLK SDAT DCDC3 STEP-DOWN CONVERTER VLDO1 VLDO2 200-mA LDO 200-mA LDO THERMAL SHUTDOWN CONTROL VINDCDC2 L2 VDCDC2 DEFDCDC2 VINDCDC3 L3 VDCDC3 VINLDO VLDO1 VLDO2 DEFDCDC3 UVLO VREF OSC HOT_RESET RESPWRON PWRFAIL VCC PGND2 PGND3 AGND2 AGND1 DEFLDO2 DEFLDO1 DCDC1 STEP-DOWN CONVER TER VINDCDC1 L1 VDCDC1 DEFDCDC1 PGND1 INT PWRFAIL_SNS VRTC VBACKUP DCDC1_EN DCDC3_EN BBAT SWITCH VSYSIN LOWBAT_SNS LDO_EN DCDC2_EN TRESPWRON LOW_BATT VCC TPS65022 www.ti.com SLVS667B – JULY 2006 – REVISED JANUARY 2016 7 Detailed Description 7.1 Overview TPS65022 has 5 regulator channels, 3 DCDCs and 2 LDOs. DCDC3 has dynamic voltage scaling feature, DVS, that allows for power reduction to CORE supplies during idle operation or over voltage during heavy duty operation. With DVS and 2 more DCDCs plus 2 LDOs, the TPS65022 is ideal for CORE, Memory, IO, and peripheral power for the entire system of a wide range of suitable applications. The device incorporates enables for the DCDCs and LDOs, I2C for device control, pushbutton and a reset interface that complete the system and allow for the TPS65022 to be adapted for different kinds of processors or FPGAs. For noise sensitive circuits, the DCDCs can be synchronized out of phase from one another, reducing the peak noise at the switching frequency. Each converter can be forced to operate in PWM mode to ensure constant switching frequency across the entire load range. However, for low load efficiency performance the DCDCs automatically enter PSM mode, which reduces the switching frequency when the load current is low, saving power at idle operation. 7.2 Functional Block Diagram Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPS65022 |
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Similar Description - TPS65022_16 |
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