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TPS65020RHAR Datasheet(PDF) 12 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 12 Page - Texas Instruments |
12 / 53 page t DEGLITCH HOT_RESET RESPWRON V DCDC3 O defaultvoltage anyvoltageset withI Cinterface 2 t NRESPWRON TPS65020 SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics: VDCDC3 Step-Down Converter (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Adjustable output voltage with resistor VINDCDC3 = VDCDC3 +0.4 V (min 2.5 V) to –2% 2% divider at DEFDCDC3 FPWMDCDC3=0 6 V; 0 mA ≤ IO ≤ 600 mA Adjustable output voltage with resistor VINDCDC3 = VDCDC3 +0.4 V (min 2.5 V) to –1% 1% divider at DEFDCDC3; FPWMDCDC3=1 6 V; 0 mA ≤ IO ≤ 600 mA VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) Line Regulation 0% V to 6 V; IO = 10 mA Load Regulation IO = 10 mA to 400 mA 0.25% A VDCDC3 ramping from 5% to 95% of target Soft-start ramp time 750 μs value Internal resistance from L3 to GND 1 M Ω VDCDC3 discharge resistance 300 Ω 7.11 Timing Requirements over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT fMAX Clock frequency 400 kHz twH(HIGH) Clock high time 600 ns twL(LOW) Clock low time 1300 ns tR DATA and CLK rise time 300 ns tF DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 300 ns tsu(DATA) Data input setup time 300 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns Figure 1. HOT_RESET Timing 12 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: TPS65020 |
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