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TPS65020RHAR Datasheet(PDF) 40 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 53 page  I RMSCout + 1 * Vout Vin L ƒ 1 8 Cout ƒ ) ESR I RMSCout + 1 * Vout Vin L ƒ 1 2 3 TPS65020 SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 www.ti.com (10) At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: where • the highest output voltage ripple occurs at the highest input voltage Vin (11) At light-load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. 9.2.2.3 Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10- μF ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the DC-DC converters. A filter resistor of up to 10R and a 1- μF capacitor is used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold because up to 3 mA can flow through this resistor into the VCC pin when all converters are running in PWM mode. Table 17. Possible Capacitors CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS 22 μF 1206 TDK C3216X5R0J226M Ceramic 22 μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic 10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 μF 0805 TDK C2012X5R0J106M Ceramic 22 μF 0805 TDK C2012X5R0J226MT Ceramic 22 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 9.2.2.4 Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See the table for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 38. The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3 does not change the voltage set with the register. Bit B6 in the CON_CTRL2 register is used to switch between the internal voltage setting or the voltage set with the external DEFDCDC3 pin for the VDCDC3 converter. Table 18. Voltage Options PIN LEVEL DEFAULT OUTPUT VOLTAGE VCC 3.3 V DEFDCDC1 GND 3 V VCC 2.5 V DEFDCDC2 GND 1.8 V VCC 1.55 V DEFDCDC3 GND 1.3 V 40 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: TPS65020 |
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