TPS65020RHAR datasheet(34/53 Pages) TI1

Part #	TPS65020RHAR

Description	Power Management IC

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Manufacturer	TI1 [Texas Instruments]

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TPS65020

SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016

www.ti.com

8.6.7 DEFCORE. Register Address: 06h (Read and Write), Default Value: 14h/1Eh

Table 10. DEFCORE Register

DEFCORE

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

–

CORE4

CORE3

CORE2

CORE1

CORE0

function

Default

0

1

DEFDCDC3

1

DEFDCDC3

0

Default value

–

RESET(1)

loaded

Read/Write

–

R/W

RESET(1): DEFCORE is reset to its default value by one of these events:

•

undervoltage lockout (UVLO)

•

DCDC1 AND DCDC3 disabled

•

HOT_RESET pulled low

•

RESPWRON active

•

VRTC below threshold

Table 11. DCDC3 DVS Voltages

CORE4

CORE3

CORE2

CORE1

CORE0

VDCDC3

CORE4

CORE3

CORE2

CORE1

CORE0

VDCDC3

0

0.8 V

1

0

1.2 V

0

1

0.825 V

1

0

1

1.225 V

0

1

0

0.85 V

1

0

1

0

1.25 V

0

1

0.875 V

1

0

1

1.275 V

0

1

0

0.9 V

1

0

1

0

1.3 V

0

1

0

1

0.925 V

1

0

1

0

1

1.325 V

0

1

0

0.95 V

1

0

1

0

1.35 V

0

1

0.975 V

1

0

1

1.375 V

0

1

0

1 V

1

0

1.4 V

0

1

0

1

1.025 V

1

0

1

1.425 V

0

1

0

1

0

1.05 V

1

0

1

0

1.45 V

0

1

0

1

1.075 V

1

0

1

1.475 V

0

1

0

1.1 V

1

0

1.5 V

0

1

0

1

1.125 V

1

0

1

1.525 V

0

1

0

1.15 V

1

0

1.55 V

0

1

1.175 V

1

1.6 V

8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h

Table 12. DEFSLEW Register

DEFSLEW

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

–

SLEW2

SLEW1

SLEW0

function

Default

–

1

0

Default value

–

UVLO

loaded

Read/Write

–

R/W

34

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