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TPS65020RHAR Datasheet(PDF) 31 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 53 page  TPS65020 www.ti.com SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 1 = indicates that the LDO1 output voltage is below its target regulation voltage 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1 masks PGOODZ<n>. Table 5. MASK Register MASK B7 B6 B5 B4 B3 B2 B1 B0 Bit name and MASK MASK MASK MASK MASK MASK MASK – function PWRFAILZ LOWBATTZ VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1 Default 1 1 0 0 0 0 0 0 Default value UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO loaded Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The contents of the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low. Table 6. REG_CTRL Register REG_CTRL B7 B6 B5 B4 B3 B2 B1 B0 Bit name and – – VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1 – function ENABLE ENABLE ENABLE ENABLE ENABLE Default 1 1 1 1 1 1 1 – Set by signal – – DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ LDO_ENZ LDO_ENZ – Default value – – – UVLO UVLO UVLO UVLO UVLO loaded Read/Write – – R/W R/W R/W R/W R/W – Bit 5 VDCDC1 ENABLE DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high. Bit 4 VDCDC2 ENABLE DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high. Bit 3 VDCDC3 ENABLE DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high. Bit 2 LDO2 ENABLE LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high. Bit 1 LDO1 ENABLE Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: TPS65020 |
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