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TPS65020RHAR Datasheet(PDF) 26 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 53 page  TPS65020 SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 8.3.9 Low-Dropout Voltage Regulators The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the LDO_EN pin, both LDOs can be disabled or programmed through the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65020 step-down and LDO voltage regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction temperature rises above 160°C. 8.3.10 Undervoltage Lockout The undervoltage lockout circuit for the five regulators on the TPS65020 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note that when any of the DC-DC converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. This current must be taken into consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS65020 internal analog circuitry supply. 8.3.11 Power-Up Sequencing The TPS65020 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2. Table 2. Control Pins and Status Outputs for DC-DC Converters PIN NAME INPUT FUNCTION OUTPUT Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to DEFDCDC3 I 1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V. Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to DEFDCDC2 I 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V. Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V, DEFDCDC1 I DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V. DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65020 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of HOT_RESET I VDCDC3 to its default value defined with the DEFDCDC3 pin. A 1-M Ω pullup resistor to VCC is integrated in TPS65020. HOT_RESET is internally de-bounced by the TPS65020. RESPWRON is held low when power is initially applied to the TPS65020. The VRTC voltage is monitored: RESPWRON O RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms. 8.4 Device Functional Modes The TPS6502x devices are either in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold, 2.35 V (typically). Once the voltage at VCC has increased above UVLO, the device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use. 26 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: TPS65020 |
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