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TPS65020RHAR Datasheet(PDF) 25 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 53 page  ( ) min min max DS(on) L Vin Vout Iout r R = + ´ + TPS65020 www.ti.com SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 Feature Description (continued) These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light-load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed-frequency PWM mode. 8.3.4 Low Ripple Mode Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the DC-DC converters if operated in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low output current. 8.3.5 Soft-Start Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The soft-start is realized by using a very low current to initially charge the internal compensation capacitor. The soft- start time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 μs between the converter being enabled and switching activity starting. The delay allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft-start ramp catches up with the output voltage. 8.3.6 100% Duty Cycle Low-Dropout Operation The TPS65020 converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage. It is calculated in Equation 7. where • Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions) • rDS(on)max = maximum P-channel switch rDS(on) • RL = DC resistance of the inductor • Voutmin = nominal output voltage minus 2% tolerance limit (7) 8.3.7 Active Discharge When Disabled When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDCx_EN, or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled through the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300- Ω (typical) load which is active as long as the converters are disabled. 8.3.8 Power-Good Monitoring All three step-down converters and both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register through the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good. Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TPS65020 |
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