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TPS65020RHAR Datasheet(PDF) 24 Page - Texas Instruments |
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TPS65020RHAR Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 53 page  PFMDCDC3 VINDCDC3 I leave = 29 W PFMDCDC2 VINDCDC2 I leave = 20 W PFMDCDC1 VINDCDC1 I leave = 18 W PFMDCDC3 VINDCDC3 I enter = 39 W PFMDCDC2 VINDCDC2 I enter = 26 PFMDCDC1 VINDCDC I enter = 24 1 TPS65020 SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) The step-down converter outputs (when enabled) are monitored by power-good (PG) comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged through on-chip 300- Ω resistors when the DC-DC converters are disabled. This feature can be enabled using the I2C interface. During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead-time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. The three DC-DC converters operate synchronized to each other with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three converters can be changed using the CON_CTRL register. 8.3.3 Power Save Mode Operation As the load current decreases, the converters enter the power save mode operation. During PSM, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency. To optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated using the equations in Equation 1, Equation 2, and Equation 3. (1) (2) (3) During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined using the equations in Equation 4, Equation 5, and Equation 6. (4) (5) (6) If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1. the output voltage drops 2% below the nominal VO due to increasing load current 2. the PFM burst time exceeds 16 × 1 / fs (10.67 μs typical). 24 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: TPS65020 |
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