 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TPS65020 Datasheet(PDF) 8 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TPS65020 Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 53 page  TPS65020 SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT ILK Leakage current Output inactive high 0.1 μA VLDO1 AND VLDO2 LOW-DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V VO LDO2 output voltage range 1 3.3 V Maximum output current for LDO1, IO 200 mA LDO2 LDO1 and LDO2 short-circuit I(SC) VLDO1 = GND, VLDO2 = GND 400 mA Current limit IO = 50 mA, VINLDO = 1.8 V 120 Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.5 V 65 150 mV IO = 200 mA, VINLDO = 1.8 V 300 Output voltage accuracy for LDO1, IO = 10 mA –2% 1% LDO2 VINLDO1,2 = VLDO1, 2 + 0.5 V Line regulation for LDO1, LDO2 –1% 1% (min. 2.5 V) to 6.5 V, IO = 10 mA Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC V VIL Low level input voltage 0 0.1 V IH Input bias current 0.001 0.05 μA LOGIC SIGNALS PB_IN; PB_OUT VOL Low level output voltage at PB_OUT IOL = 20 mA 0.5 V VOH High level output voltage PB_OUT 6 V VIL Low level input voltage PB_IN 0.4 V VIH High level input voltage PB_IN 1.3 VCC (2) V II Input leakage current PB_IN 1 μA THERMAL SHUTDOWN T(SD) Thermal shutdown Increasing junction temperature 160 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDERVOLTAGE LOCK OUT UVLO Internal UVLO VCC falling –2% 2.35 2% V V(UVLO_HYST) Internal UVLO comparator hysteresis 120 mV VOLTAGE DETECTOR COMPARATORS Comparator threshold Falling threshold –1% 1.0 1% V (PWRFAIL_SNS, LOWBAT_SNS) Hysteresis 40 50 60 mV Propagation delay 25-mV overdrive 10 μs POWER-GOOD VDCDC1, VDCDC2, VDCDC3, VLDO1, V(PGOODF) –12% –10% –8% VLDO2, decreasing VDCDC1, VDCDC2, VDCDC3, VLDO1, V(PGOODR) –7% –5% –3% VLDO2, increasing (2) The input voltage can go as high as 6 V. If the input voltage exceeds VCC, an input current of (V(PB_IN) – 0.7 V – VCC) / 10 kΩ flows. 8 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: TPS65020 |
Similar Part No. - TPS65020_16 |
|
Similar Description - TPS65020_16 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
