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TPS40322RHBT Datasheet(PDF) 20 Page - Texas Instruments |
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TPS40322RHBT Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 47 page  ´ = 9 RT SW 20 10 R f TPS40322 SLUSAF8E – JULY 2011 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 7.3.7.2 Prebiased Output Start-Up The TPS40322 contains a circuit that prevents current from being pulled from the output during the start-up sequence in a pre-biased output condition. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FBx pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier input, the device slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre- biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and controlled. DESIGN NOTE During the soft-start sequence, when the PWM pulse width is shorter than the minimum controllable on-time, which is generally caused by the PWM comparator and gate driver delays, pulse skipping may occur and the output might show larger ripple voltage. 7.3.7.3 Shutdown During the shutdown sequence, BP6 is controlled by ENx/SSx. If both of ENx/SSx pins are pulled low, BP6 is turned off regardless of the input voltage remaining higher than the programmed UVLO threshold. 7.3.8 Switching Frequency and Master or Slave Synchronization The switching frequency is set by the value of the resistor connected from the RT pin to AGND. The RT resistor value is calculated in Equation 5. where • RRT is the the resistor from RT pin to AGND, in Ω • fSW is the desired switching frequency, in Hz (5) The TPS40322 device can also synchronize to an external clock that is ±20% of the master clock frequency which is two times the free running frequency. Each TPS40322 can be set by the PHSET pin as either master or slave. The master produces a 50% duty cycle clock to the slave. The slave synchronizes to the external clock with 50% duty cycle and selects the phase shift angle as shown in Table 1. Figure 21 shows an example of synchronizing two TPS40322 devices to generate an evenly distributed shift to reduce input ripple. Table 1. Phase Shift Angle Selection PHSET PHASE ANGLE (°) MODE RANGE CONNECTION CH1 CH2 (V) AGND < 0.5 Master 0 180 Floating 0.6 to 2 Slave 0 180 High > 2.1 Slave 90 270 20 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS40322 |
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