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TPS40322 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS40322 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 47 page  TPS40322 www.ti.com SLUSAF8E – JULY 2011 – REVISED JANUARY 2016 Pin Functions (continued) PIN I/O DESCRIPTION NAME PIN Logic level input which starts or stops CH2. Letting this pin float turns CH2 on. Pulling this pin low disables CH2. This is also the soft-start programming pin. A capacitor connected from this pin to AGND programs the soft-start time. The capacitor is charged with an internal current source of 10 μA. The resulting voltage EN2/SS2/GSNS 10 I ramp of this pin is also used as a second non-inverting input to the error amplifier 2 after a 0.8 V (typical) level shift downwards. In two-phase mode, this pin becomes GSNS as the negative terminal of a remote sense amplifier. Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal FB1 4 I reference voltage. Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal FB2 8 I reference voltage. Connecting the FB2 pin to the BP6 pin enables two-phase mode and disables the error amplifier 2. Bootstrapped gate drive output for the high-side N-channel MOSFET for CH1. A 2- Ω resistor is HDRV1 24 O recommended for a noisy environment. Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2. A 2- Ω resistor is HDRV2 16 O recommended for a noisy environment. Used to set the overcurrent limit for CH1 with 10 μA of current flowing through a resistor from this pin to ILIM1 30 I AGND. Used to set the overcurrent limit for CH2 with 10 μA of current flowing through a resistor from this pin to ILIM2/VSNS 11 I AGND. In two-phase mode, this pin becomes VSNS as the positive terminal of a remote sense amplifier. LDRV1 22 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1. LDRV2 18 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2. PG1 27 O Open drain power good indicator for CH1 output voltage. PG2 14 O Open drain power good indicator for CH2 output voltage. Power ground 1. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce PGND1 21 — channel to channel interference. Power ground 2. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce PGND2 19 — channel to channel interference. Used to set master or slave mode and phase angles. The master emits a 50% duty clock to the slave. The PHSET 32 I slave synchronizes to the external clock and select the phase shift angle. RT 2 I Connect a resistor from this pin to AGND to set the oscillator frequency. SW1 23 I Connect to the switched node on converter CH1. It is the return for the CH 1 high-side gate driver. SW2 17 I Connect to the switched node on converter CH2. It is the return for the CH 2 high-side gate driver. In master mode, a 2x free running frequency clock is sent out on SYNC pin. In slave mode, sync to an external clock which is ±20% of the free running MASTER_CLOCK frequency. The MASTER_CLOCK SYNC 1 I/O frequency is 2x of the free running frequency (set by RT) and operates at 50% duty cycle. When not being used, SYNC must be left floating. UVLO 31 I A resistor divider from VIN determines the input voltage that the controller starts. Power input to the controller. A low ESR bypass ceramic capacitor of 0.1 μF or greater must be connected VDD 26 I closely from this pin to AGND. Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS40322 |
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