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TPS40322 Datasheet(PDF) 31 Page - Texas Instruments |
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TPS40322 Datasheet(HTML) 31 Page - Texas Instruments |
31 / 47 page ![]() 100 1000 10000 100000 1000000 −60 −40 −20 0 20 40 60 80 100 −135 −90 −45 0 45 90 135 180 225 Frequency (Hz) Gain Phase G001 100 1000 10000 100000 1000000 −60 −40 −20 0 20 40 60 80 100 −135 −90 −45 0 45 90 135 180 225 Frequency (Hz) Gain Phase G001 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 Output Current (A) VIN = 8 V VIN = 12 V VIN = 15 V VOUT = 1.2 V G001 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 Output Current (A) VIN = 8 V VIN = 12 V VIN = 15 V VOUT = 1.8 V G001 ( ) ( ) ( ) ( ) UVLO(max) UVLO set UVLO hys UVLO(on _ min) UVLO(max) V 1.25 V R R 68.1k 12.6k 12.7k 8.0 V 1.25 V V V > ´ = W = W » W - - ( ) ( ) ( ) UVLO on UVLO off UVLO hys UVLO V V 8 V 7 V R 66.7k 68.1k I 15 A - - = = = W » W m TPS40322 www.ti.com SLUSAF8E – JULY 2011 – REVISED JANUARY 2016 8.2.1.2.11.7 UVLO Programming Resistors (R1 and R3) The UVLO hysteresis level is programmed by R1 with Equation 28 and Equation 29. (28) (29) 8.2.1.2.11.8 VDD Bypass Capacitor (C2) As shown in the Pin Configuration and Functions section, use a 0.1-µF, 50-V, X7R capacitor for VDD bypass. 8.2.1.2.11.9 VBP6 Bypass Capacitor (C18) Select a 3.3-µF (or greater) low ESR capacitor for BP6. For this design use a 3.3-µF, X5R ceramic capacitor. 8.2.1.3 Application Curves Figure 24. Efficiency vs Load Current (8 V to 15 V to 1.2 V Figure 25. Efficiency vs Load Current (8 V to 15 V to 1.8 V at 10 A, Design Example 1) at 10 A, Design Example 1) Figure 26. Design Example 1 Loop Response Figure 27. Design Example 1 Loop Response VIN = 12 V, VOUT1 = 1.2 V, IOUT1 = 10 A, 80-kHz Bandwidth, VIN = 12 V, VOUT2 = 1.8 V, IOUT2 = 10 A, 80-kHz Bandwidth, 50° Phase Margin 50° Phase Margin Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: TPS40322 |
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